For over a decade, the global semiconductor industry relied on the FinFET (Fin Field-Effect Transistor) architecture to push computing from 22nm down to 3nm. In FinFET designs, a thin silicon fin is surrounded on three sides by a conducting gate. However, as transistor gate lengths scaled below 3nm, quantum mechanical short-channel leakage and source-to-drain tunneling overwhelmed the electrostatic control of three-sided gates.
To extend Moore’s Law into the 2nm regime and beyond, foundries like TSMC, Intel, and Samsung have executed the most difficult architectural transition in semiconductor history: Gate-All-Around (GAAFET) Nanosheets.
Figure 7: Cross-Sectional Comparison of FinFET vs Gate-All-Around (GAAFET) Nanosheet Channels.
The Physics of Nanosheet Electrostatics
In a GAAFET design, the vertical fin is replaced by horizontally stacked ribbons of silicon completely encapsulated on all four sides by the dielectric gate material.
- Superior Electrostatic Control: Four-sided gate wrapping eliminates sub-threshold leakage currents.
- Variable Channel Width Tuning: Designers can widen individual nanosheet ribbons to maximize drive current for high-frequency CPU cores, or narrow them to slash static power consumption in mobile processors.
- High-NA Extreme Ultraviolet (EUV) Lithography: Using ASML’s 0.55 Numerical Aperture scanners to print circuit features at single-exposure 8nm resolutions.
